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Computer Science
(24-2) Generative AI
GenAI 01 - Representations
GenAI 02 - Autoregressive Models
GenAI 03 - Maximum Likelihood Learning
Generative AI
(24-2) Scalable High Performance Computing
Double buffering
Scalable High Performance Computing
SHPC 01 - Trends
SHPC 02 - Binary Representations
SHPC 03 - Floating Point Representations
SHPC 04 - Processes and Threads
SHPC 05 - Dependences and Pipelining
SHPC 06 - Loop-Carried Dependences and Parallelism
SHPC 07 - Synchronization
SHPC 09 - GPU Architectures
SHPC 10 - Caches
SHPC 11 - Cache Coherence and Tiling
SHPC 12 - Memory Consistency and Virtual Memory
SHPC 13 - OpenCL
SHPC 13 - OpenMP
SHPC 14 - CUDA
SHPC 15 - MPI
SHPC 16 - Register Allocation
SHPC 17 - Multiple GPUs
SHPC 17.5 - Multiple GPUs (CUDA)
SHPC 18 - CUDA Streams
SHPC 19 - Optimization for GPUs
SHPC 20 - Shared Memory
SHPC 21 - AI parallelism
Computer Architecture (RISC-V)
Arithmetic & Logical Operations
Byte Ordering
Computer Architecture (RISC-V)
Conditional Operations
CPU (Central Processing Unit)
Design Principles
Floating points
ISA (Instruction Set Architecture)
Logical core
Memory Operations
Procedure Call
Register vs Memory
RISC vs CISC
RISC-V Addressing
RISC-V Data Types
RISC-V Instruction Set
RISC-V Registers
Theoretical Peak Performance
The Moonmath manual to zk-snarks
3. Arithmetics
3. Arithmetics
3.2 Integer Arithmetic
The MoonMath Manual to ZK-SNARKS
Computer Science
Consensus
Balancing Attack
Bouncing Attack
Consensus
FOCIL
Lock and Commit
Network Model
Nothing-at-Stake
Partially synchronous network model
Paxos
Proposer Boost
Reorg Attack
Synchronous network model
Cryptography
Cryptography
Paper Review
(CCS '23) TrustBoost-Boosting Trust among Interoperable Blockchains
(CCS '24) Lutris - A Blockchain Combining Broadcast and Consensus
(ICDE '23) Scaling Blockchain Consensus via a Robust Shared Mempool
(PODC '19) HotStuff-BFT Consensus with Linearity and Responsiveness
(Security '24) Max Attestation Matters - Making Honest Parties Lose Their Incentives in Ethereum PoS
(VLDB '23) ZKSQL - Verifiable and Efficient Query Evaluation with Zero-Knowledge Proofs
Paper Review
Session note
(Ethereum) Pectra & Fusaka Upgrade
Enterprise Blockchain Solutions
Session Note
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Computer Architecture (RISC V)
Folder: Computer-Science/Computer-Architecture-(RISC-V)
18 items under this folder.
Dec 31, 2024
Theoretical Peak Performance
Dec 31, 2024
Register vs Memory
Dec 31, 2024
RISC-V Registers
Dec 31, 2024
RISC-V Instruction Set
Dec 31, 2024
RISC-V Data Types
Dec 31, 2024
RISC-V Addressing
Dec 31, 2024
RISC vs CISC
Dec 31, 2024
Procedure Call
Dec 31, 2024
Memory Operations
Dec 31, 2024
Logical core
Dec 31, 2024
ISA (Instruction Set Architecture)
Dec 31, 2024
Floating points
Dec 31, 2024
Design Principles
Dec 31, 2024
Conditional Operations
Dec 31, 2024
Computer Architecture (RISC-V)
Dec 31, 2024
CPU (Central Processing Unit)
Dec 31, 2024
Byte Ordering
Dec 31, 2024
Arithmetic & Logical Operations